1. Field of the Invention
The present invention relates to high-speed microprocessors in personal computer systems, and more particularly to techniques for controlling the speed of a high-speed microprocessor with an internal cache to achieve software compatibility with existing application programs, which, because of their specific hardware dependency, cannot be run at a higher speed.
2. Description of Prior Art
The personal computer industry is a vibrant and growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful personal computers. Another major factor in the success of the personal computer industry has been the concern on the part of system designers to maintain compatibility between the newer systems that are being developed and the older systems that are currently on the market or in use.
The introduction of the personal computer has resulted in a tremendous amount of applications programs written for both the professional and the home entertainment markets. These personal computers are designed around commercially available microprocessor chip sets which may include a plurality of microprocessors connected in an architecture which results in varying degrees of execution rates.
A microprocessor chip set widely used by personal computer manufacturers is the Intel Corporation 8086 family of microprocessors. This family includes: the 8088 microprocessor; the 8086 microprocessor; the 80286 microprocessor; the 80386 microprocessor; and now the 80486 microprocessor--all having similar instruction sets. The 80486 is the latest generation of the Intel 8086 family of microprocessors and it has a higher execution cycle rate than its predecessors, almost twice as fast as the 80386 in certain operations. A new feature introduced in the 80486 microprocessor is an 8 kbyte internal cache that it may access without requesting the local bus.
With the availability of a software compatible microprocessor (i.e., executes the same instruction sets), it is possible to upgrade a prior art personal computer to a personal computer with a higher execution speed and maintain compatibility with most application programs written for the lower speed microprocessor chip sets. While faster, software compatible microprocessors are available, it is not possible, however, to simply substitute the faster microprocessor for the slower microprocessor in some cases and thereby produce a personal computer which executes at a higher speed for all of the application programs written for the slower microprocessor.
Not all application programs written for slower microprocessors are capable of running at faster microprocessor speeds even though each instruction in the program is executed in a logically similar manner in these machines. The inability to run some programs at higher speeds results from the fact that programmers, when writing application programs for the slower microprocessors, took advantage of the particular execution cycle time of the microprocessor in structuring routines which were time dependent. Running a program that is dependent on a particular execution speed at higher instruction execution speeds changes the resulting time intervals and thereby renders the program non-functional.
It has also been discovered that many of the currently used copy-protected schemes currently employed by many software writers are dependent on microprocessor clock rates. Many of the new personal computers employing some of the later generation microprocessors with high clock rates cannot utilize the copy-protected software without data transfer errors because these copy-protected programs do not function properly whenever the instruction execution speeds change.
At first blush, changing the frequency of the clock signal applied to the microprocessor would appear to resolve the problem. For example, it is possible to provide a personal computer having an Intel 80486 microprocessor or other high speed microprocessor rather than a slower microprocessor and run the high speed microprocessor at different clocking frequencies: high speeds for those application programs which can run at the higher speeds and slower speeds for those application programs which are time dependent. Unfortunately, this simple clocking speed change does not result in a personal computer which is software compatible for all varieties of application programs.
A change of the clock rate will not suffice to make many of the older software compatible because of the many other machine functions which may be affected. Even though the previous microprocessor chip sets, (i.e. 8086, 8088, 80286, 80386, and 80486) are software compatible, the internal design of the microprocessors is not the same.
One internal design difference between these microprocessors is the amount of prefetch buffer memory provided in the microprocessor as well as the rate at which bytes are fetched from memory. In the Intel 8088 there are four bytes of prefetch queue, in the 8086 there are six bytes of prefetch queue, in the 80286 there are eight bytes of prefetch queue, in the 80386 there are 16 bytes of prefetch queue, and in the 80486 there are 32 bytes of prefetch queue. Each microprocessor is designed to keep its prefetch queue full of information in order that the microprocessor can continue to execute code, which on the average, achieves a desired execution throughput rate. When program jumps occur, the contents of the prefetch buffer are lost. This loss of information is reflected in wasted execution time because of the time required to obtain the prefetch information that is discarded at the time the program jump occurs. The time required to obtain the prefetch information is dependent on the rate at which data is fetched from memory, which varies among the various processors in the Intel family. It is because of this difference in the prefetch buffer capacity and the rate at which data is fetched from memory that a high speed microprocessor runs at a different speed for the same application program when the microprocessor is run at the same clocking frequency as is normally used for a slower microprocessor.
This difference in internal design, coupled with the particular design of the application program, i.e., does it contain a lot of program jumps, affects the execution speed of a given application program. Therefore, the execution time at the high speed for the high speed microprocessor is not necessarily proportionally faster than the execution time when the microprocessor clock rate is set to the slower normal frequency for the slow speed microprocessor. Stated differently, reducing the microprocessor clock rate of a high speed microprocessor while keeping all else the same does not result in the same execution time for a given application program to run on the high speed microprocessor as occurs if the same program is run on the slow speed microprocessor.
Therefore, it would be advantageous to provide a personal computer which provides for a high speed microprocessor to execute application programs which are not time dependent at high speeds, but provides a lower speed execution for those application programs which are time dependent so that the time dependent application programs appear to be running at substantially the same execution speed as they would have run on the microprocessor for which they were written.
Computer designers have used various methods to overcome the software compatibility problems that result from running execution cycle-time dependent software on higher speed microprocessors. Many IBM-compatible computers include logic that generates a slowdown signal which is asserted when the processor is to be slowed down for software compatibility reasons. The slowdown signal is used in conjunction with a means for halting the operation of the high speed microprocessor during the time that the slowdown signal is asserted so that it may more closely conform to the speed of the slower speed microprocessor. One such means includes placing the microprocessor in a hold state and controlling the length of the hold state of the processor to achieve the desired result. While a microprocessor is placed in a hold state, it is prevented from accessing the local bus during that time and is therefore slowed down.
This method has generally proved satisfactory. However, the 80486 microprocessor can continue operation when it is placed in an external hold state because it may still draw instructions and data from its internal cache. Therefore, a new method is necessary to slow down the 80486 microprocessor in order to prevent it from accessing its internal cache during a slowdown and to insure that the central processing unit is actually halted.
Another important consideration is that the processor be able to respond to hold requests during a slowdown to allow requesting bus masters as well as other bus requesting devices access to the bus and thereby prevent possible latency problems from developing. For example, if a device required the bus, the system arbiter would assert a processor hold request PHOLD to the processor. The processor must respond with a processor hold acknowledge signal PHLDA in order for the arbiter to be able to grant control of the bus to the device to prevent any possible latency problems from developing. If the processor does not respond with the HLDA signal within a given time, the time may exceed allowable limits and data may be lost, for example, by the floppy disk controller.